Clock partitioning for testability
نویسندگان
چکیده
An implementation of a design for testability model for sequential circuits is presented. The jlip-jlops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complezity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented.
منابع مشابه
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability
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